PM7347
PMC-Sierra,Inc.
S/UNI-JET
SATURN User Network Interface for J2/E3/T3
• Implements the Physical Layer
• Provides performance monitoring
counters suitable for accumulation
periods up to one second.
• Provides an 8-bit microprocessor
interface for configuration, control, and
status monitoring.
• Provides a standard 5-signal P1149.1
JTAG test port for boundary scan
board-test purposes.
• Low power 3.3 V CMOS technology
with 5 V-tolerant inputs.
• Available in a high density 256-pin
SBGA package (27 mm by 27 mm).
• Rated for industrial temperature
operation.
FEATURES
Convergence Protocol (PLCP) for T1
• Single-chip ATM User Network
and DS3 transmission systems
Interface (UNI) operating at 44.736
according to the ATM Forum UNI
Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s
conforming to ATMF-95-1207R1,
ATMF-94-0406R5, and
AF-PHY-0029.000.
Specification and ANSI
TA-TSY-000773, TA-TSY-000772, and
for E1 and E3 transmission systems
according to ETSI 300-269 and ETSI
• Provides on-chip DS3, E3 (G.751 and
300-270.
G.832), and J2 framers. Can be
configured for use solely as a framer.
• Implements the ATM physical layer for
broadband ISDN according to ITU-T
When configured in framer mode,
Recommendation I.432.
gapped transmit and receive clocks
• Uses the PM4341 T1XC, PM6341
can be generated for interfaces that
E1XC, PM4351 COMET, and framer/
need access only to payload data bits.
line interface chips for T1 and E1
• Supports bypass of the internal
applications.
framers and supports connections to
• Provides seamless interface to the
an arbitrary-rate external transmission
VORTEX DSLAM chipset,
APPLICATIONS
system interface up to a rate of 52
Mbit/s. This lets the S/UNI-JET be
used as an ATM cell delineator.
• Implements ATM direct-cell mapping
into T1, DS3, E1, E3, and J2
transmission systems according to
ITU-T Recommendation G.804.
• Provides a SCI-PHY and 50 MHz
UTOPIA Level 2 compatible 8- or
16-bit ATM-PHY Interface.
®
• DSLAM Uplinks
S/UNI -ATLAS, and
S/UNI-RCMP-200.
• Enterprise ATM/PPP Uplinks
• ATM or Frame Relay Switches,
Multiplexers, and Routers
• DS3/E3/J2 PPP Internet Access
Interfaces
• Provides programmable
pseudo-random test pattern
generation, detection, and analysis
features.
• Provides integral transmit and receive
HDLC controllers with 128-byte FIFO
depths.
• DS3/E3/J2 Frame Relay Interfaces
BLOCK DIAGRAM
SIG T1: TPOHINS
SIG T2: TPOH/TDAT
SIG T3: TIOHM/TFP/TMFP
SIG T4: TICLK
SIG T5: TPOHCLK
SIG T6: TPOHFP/TFPO/TMFPO/TGAPCLK/TCELL
SIG T7: REF8KI
1/2 TTB
Transmit
XBOC
Receive
TDFR
Receive
Transmit
IEEE
P1149.1
DTCA
TDAT [15:0]
TPRTY
SPLT
Transmit
ATM and
PLCP
TRAN
J2, E3 OR DS3
TNEG/TOHM
TPOS/TDATO
TCLK
TSOC
TCA
Line
TXCP_50
Transmit
TXFF
Transmit
TADR [2:0]
TENB
Framer
TFCLK
PHY_ADR[2:0]
ATM8
RFCLK
System
ATMF/SPLR
Receive
ATM and
PLCP
RCLK
RPOS/RDAT
FRMR
J2, E3 or DS3
RXFF
Receive
4-Cell
Line
RXCP_50
Receive
RENB
RADR [2:0]
RCA
RNEG/RLCV/ROHM
Framer
RSOC
RPRTY
RDAT [15:0]
DRCA
MPIF
Microprocessor
RBOC
Receive
RFDL
Receive
PMON
Perfor-
mance
Receive
O/H
1/2 TTB
Receive
CCPM
PLCP/cell
SIG R1: FRMSTAT
SIG R2: RPOCHCLK/
RSCLK/RGAPCLK
SIG R3: REF8KO/
RPOHFP/RFPO/RMFPO
SIG R4: RPOH/ROVRHD
SIG R5: LCD/RDATO
PMC-990996 (R2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ꢀ 1999 PMC-Sierra, Inc.
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